1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device operating in synchronism with a clock and a method for controlling the duty of the clock. For example, the present invention relates to a method for controlling the duty of the clock in a processor core including a critical path that is active while the clock is at an “H” level and a critical path that is active while the clock is an “L” level.
2. Description of the Related Art
In recent years, the operating speed of semiconductor integrated circuits (LSI) has been remarkably increased. With the increased operating speed of the semiconductor integrated circuits, processors have been commonly used which operate in synchronism with both rising edge and falling edge of a clock.
In LSIs using these processors, the duty of the clock has a significant effect on the operation characteristics, yield, and the like of the LSI. It is thus important to appropriately adjust the duty, and relevant proposals have been made by, for example, Jpn. Pat. Appln, KOKAI Publication No. 2005-159613 and Jpn. Pat. Appln. KOKAI Publication No. 2004-088434.
However, these conventional techniques are not sufficient in terms of the appropriate adjustment of the duty. It has thus been difficult to further improve the operating speed of LSIs operating at higher frequencies.
Furthermore, systems using semiconductor devices or the like often require a basic clock having a duty of 50%. However, the optimum duty of high-speed clocks exceeding, for example, a GHz order is not always 50%. A duty of a different value is often required. Thus, a configuration for controlling the duty is disclosed in, for example, the sixth page of the specification and FIG. 8 of Jpn. Pat. Appln. KOKOKU Publication No. 7-114349.
This conventional configuration enables the duty to be controlled by varying the resistance ratio of resistance elements in a voltage setting circuit. However, the configuration requires the resistance ratio to be preset. Thus, if the duty of an input signal deviates from a set value, the duty of an output signal changes correspondingly. Obtaining the desired duty has thus been difficult.